There are numerous ways in which a dynamic random access memories (DRAMs) are traditionally constructed, using variations in process, circuit designs, and system architecture. By varying these parameters, various problems related to device size and performance can be addressed. None the less, all currently available DRAMs are generally based upon architectures which share the following disadvantageous characteristics.
First, the typical general purpose DRAM has a single data port for writing and reading data to and from addressed storage locations ("dual ported" DRAMs are available which provide two data ports, typically one random and one serial port, however, these devices are normally limited to special memory applications). Second, data writes and reads are only made to a given array on a location by location (e.g. one bit, one byte, one word) basis and only during the array active cycle. Specifically, in a "random access mode", an access (read or write) is made to a single location per row address strobe (/RAS) active cycle and in a "page mode" an access is made to a single location per column address strobe (/CAS) or master clock cycle of the row addressed during the given /RAS cycle. During the inactive cycle, the array is in precharge and no accesses can be made to that array.
Third, no method has generally been established to handle contention problems which arise when simultaneous requests for access are made to the same DRAM unit. Current techniques for handling contention problems depend on the DRAM and/or system architecture selected by the designer and range, for example, from "uniform memory-noncontention" methods to "non-uniform memory access" (NUMA) methods.
Similarly, the system architectures of personal computers (PC's) generally share a number of common features. For example, the vast majority of today's PC's are built around a single central processing unit (CPU), which is the system "master." All other subsystems, such as the display controller, disk drive controller, and audio controller then operate as slaves to the CPU. This master/slave organization is normally used no matter whether the CPU is a complex instruction set computer (CISC), reduced instruction set computer (RISC), Silicon Graphics MIPS device or Digital Equipment ALPHA device.
Present memory and PC architectures, such as those discussed above, are rapidly becoming inadequate for constructing the fast machines with substantial storage capacity required to run increasingly sophisticated application software. The problem has already been addressed, at least in part, in the mainframe and server environments by the use of multiprocessor (multiprocessing) architectures. Multiprocessing architectures however are not yet cost effective for application in the PC environment. Furthermore, memory contention and bus contention are still significant concerns in any multiprocessing system, let alone in a multiprocessing PC environment.
Thus, the need has arisen for new memories for use in high speed and/or multiprocessing systems. Preferably, such memories should have a "transparent" precharge and/or multiple random access ports. Additionally, these memories should be capable of use in addressing memory contention problems, especially those occurring in multiprocessing systems.